Studying and Designing of a multi-processor and Three-Dimensional Hybrid Interconnection Network Connected on a NoC(Multi Mesh-Hypercube Connected Ring 3D-MMHcR)

Abstract

As the number of integrated computing cores has increased over the past few decades, sub-computing technologies have evolved to maintain the required performance levels, so these cores have been combined into a single processor to enhance performance. This called for shifting and focusing more on communication issues than computing, as linking processors and memory to processors themselves has a greater impact on system performance than the applied computing power itself. All of this is achieved by optimizing the design of the network-on-Chip (NoC) that connect a large number of cores or processors to a single chip and achieve better performance standards. With this research, the 3D-MMHcR NoC interconnection network was designed to connect a large number of nuclei (nodes) on a single chip and achieve speed of transport by combining three static networks: Mesh, Ring and Hypercube, the proposed hybrid network has shown better performance improvement in varying proportions in terms of cost, diameter, throughput, bisection width, scalability, and path diversity compared to the three static networks integrated with its design.