التنفيذ الفعال لخوارزمية Rijndael في الأجهزة القابلة لإعادة البرمجة باستخدام لغة VHDL

Authors

  • محمد عيسى
  • مجد الله محمد طرّاف

Abstract

لقد أدى التطبيق المتزايد لخوارزميات التشفير لضمان أمن الاتصالات في شبكات تبادل المعطيات إلى ضرورة بناء تلك الخوارزميات باستخدام الدارات الصلبة (Hardware) وذلك بغية الوصول إلى أداء عالٍ في عملية التشفير وفك التشفير.

يقدم هذا البحث عرضاً لبناء خوارزمية Rijndael بالاعتماد على شرائح FPGA ولغة التصميم VHDL في بيئة التصميم MAX+PLUS II وذلك للمحاكاة وتحقيق الأمثلية في التركيب.

تم تقليد عملية التشفير باستخدام أسلوب التصميم المتكرر وذلك للوصول إلى أقل استهلاك ممكن من الشرائح، كما عَرض هذا العمل مقارنة بين أداء التصميم المقترح و الأعمال البرمجية المنفذة سابقاً. مع العلم أن الشريحة الهدف المستخدمة لبناء التصميم وتقييم الأداء هي من نوع ACEX1K .

 

The increasing application of cryptographic algorithms to ensure secure communications across data communication  networks has led to an ever-growing demand for high performance hardware implementations of the encryption/decryption methods.

This research investigates the Rijndael algorithm with regard to FPGA and VHDL. Altera MAX+PLUS II software is used for simulation and optimization of the synthesizable VHDL code.

The Encryption is simulated using an iterative design approach in order to minimize the hardware consumption. In this work, performance comparisons between the proposed design and previous software implementations are presented. Altera ACEX1K family devices are utilized for hardware evaluation.

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Published

2019-01-24

How to Cite

1.
عيسى م, طرّاف مام. التنفيذ الفعال لخوارزمية Rijndael في الأجهزة القابلة لإعادة البرمجة باستخدام لغة VHDL. Tuj-eng [Internet]. 2019Jan.24 [cited 2025Jan.28];29(3). Available from: https://journal.tishreen.edu.sy/index.php/engscnc/article/view/7015

Issue

Vol. 29 No. 3 (2007): العلوم الهندسية

Section

Articles

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Copyright (c) 2019 ttps://creativecommons.org/licenses/by-nc-sa/4.0/

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