Implementation of 4X4 Vedic Multiplier using GDI Technology

Authors

  • Ola Jawhara Tartous university

Abstract

In the advanced microelectronics, designers had adopt designs that achieve lower energy consumption, a smaller area, and better performance, and thus the possibility of using them in sensitive applications and systems with high efficiency. Because the multiplier is the main unit in these systems and it is known that the traditional multiplication process requires many stages and takes a long time, in this research a Vedic Multiplier was designed to complete the multiplication process quickly and smoothly.  GDI technology was also relied upon to reduce the number of transistors used, the space occupied on the chip, and the energy consumed. Simulation was done through DSCH3.5,and MICROWIND 3.5 for drawing and simulation of the layout using several technology models: CMOS 0.90nm, and CMOS 0.45nm (the techniques that used on most of the previous studies) as well as the new technologies CMOS 0.32nm We also compared the chip area and power consumed for each technology.

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Published

2024-11-03

How to Cite

1.
جوهره ع. Implementation of 4X4 Vedic Multiplier using GDI Technology. Tuj-eng [Internet]. 2024Nov.3 [cited 2024Dec.4];46(4):153-64. Available from: https://journal.tishreen.edu.sy/index.php/engscnc/article/view/17869

Issue

Vol. 46 No. 4 (2024): Tishreen University Journal of Research and Scientific Studies - Engineering Sciences Series

Section

Articles

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Copyright (c) 2024 https://creativecommons.org/licenses/by-nc-sa/4.0/

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