تصميم ونمذجة المصفوفة الانقباضية اعتماداً على لغة VHDL وتقنيةFPGA
Abstract
Systolic array design based on Field Programmable Gate Array (FPGA ) can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism, which is also naturally explored in systolic array and in implementing this design in FPGA, allows the redefinition of the interconnections and operations even during run time (dynamically).We have designed 2D systolic array architecture that implements the matrix multiplication algorithm. A VHDL for this design is applied to Xilinx FPGA. This design would be faster than the software of any alternative algorithm.
يؤدي تصميم المصفوفة الانقباضية اعتماداً على تقنية الـ FPGA إلى وضع حل فعال لِطيف واسع من المشاكل الحسابية, حيث تسمح المعالجة التفرعية الموجودة أصلاً في المصفوفة الانقباضية والمُحققة بتقنية الـ FPGA بإعادة التهيئة حتى أثناء زمن التشغيل (ديناميكياً).
قمنا بتصميم مصفوفة انقباضية ثنائية البعد تنفذ خوارزمية ضرب مصفوفتين, ثم تمت نمذجة هذا التصميم باستخدام لغة وصف الكيان الصلب للدارة المتكاملة العالية السرعة VHDL, وتم تحقيق النمذجة على لوحة مصفوفة البوابة القابلة للبرمجة من عائلة Xilinx .
إن زمن التنفيذ لهذا التصميم أسرع بكثير من أي برنامج يقوم بتنفيذ أي خوارزمية بديلة لضرب مصفوفتين.
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