Improve physical positioning algorithms within the FPGA array

Abstract

There has been a dramatic increase in the number of circuit designs that can be implemented in a single FPGA chip .The difficulties encountered by the "field-programmable gate array" (FPGA) segments are similar in nature to the problems experienced by ASIC Application Specific Integrated Circuit designs such as design and design dimensions, power loss problems and time delay in the transmission of electrical signals Between design units although the techniques used to solve ASIC problems are different from FPGAs, Solve ASIC-created FPGA problems. The search provides an adjustment to the positioning algorithm used to determine where the FPGA resources are placed "electronic elements programmed" on the chip in order to reduce the number of blocks used by the chip by modifying the VPR package used by QUARTIZ which controls Positioning and orientation algorithms. The latter specifies the distribution of the electronic elements achieved in the FPGA chip. The proposed modification reduced the number of blocks programmed by up to 30%, which reduced the energy consumption and reduced the thermal spread of the chip because these algorithms are  factor that greatly affects the thermal deployment of the chip.